In double data rate (DDR) input/output design, a delay-locked loop is often used to align the DQ clock and the DQS strobe with a reference clock signal. Such alignment is accomplished by the DLL adding to the reference clock delay chain a delay sufficient to align a leading edge of a pulse in the reference clock signal with a leading edge of a pulse in a system feedback signal. Usually, the added delay is sufficient to push the current positive feedback clock edge to the next positive reference clock edge. Such an implementation may, at times, require the addition of nearly a full clock period of delay when the positive edge of the feedback signal slightly trails the positive edge of the reference signal. Increasing the delay added to the feedback signal increases the jitter present in the power supply. Thus, DDR IO incurs power supply sensitivity issues as delay units are added to the feedback signal.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.